The present invention relates to a high-rate pulse pattern generator that, for instance, generates a pulse pattern and supplies it to an object circuit, detects an error of an output pulse pattern issued from said object circuit and measures an error rate and more particularly, to such a high-rate pulse pattern generator that parallel patterns generated from pattern generating circuits are sequentially multiplexed in multiple stages by a plurality of multiplexing circuits and issued as a high-rate pattern.
FIG. 1 shows a conventional high-rate pulse pattern generator known in the prior art. An input clock signal CK enters from an input terminal 11 into a frequency division circuit 12.sub.1 in a first stage of cascade-connected n units of 1/2 frequency division circuits 12.sub.1 -12.sub.n, and an output clock from the frequency division circuit 12.sub.n in the last stage enters a pattern generating circuit 13. Every time a clock enters into the pattern generating circuit 13, it issues data of 2.sup.n patterns parallel to each other, and said 2.sup.n parallel pattern data enter a multiplexing circuit 14.sub.1 in the first stage of n multiplexing circuits 14.sub.1 -14.sub.n connected in cascade. In each multiplexing circuit, input patterns are multiplexed every two patterns into a pattern and then issued as an output. Consequently, the number of parallel patterns becomes one half at each multiplexing circuit. Each output of the 1/2 frequency division circuit 12.sub.n, 12.sub.n-1,--or 12.sub.1 is delayed respectively in a delay circuit 15.sub.1, 15.sub.2,--or 15.sub.n while the multiplexing circuits 14.sub.1 -14.sub.n are controlled for multiplexing by each output of the delay circuits 15.sub.1 -15.sub.n, respectively. The output pattern from the multiplexing circuit 14.sub.n in the final stage is supplied to a data terminal D of a retiming circuit 16 where said output pattern is subject to retiming by the input clock signal to the input terminal 11 delayed by the delay circuit 15.sub.r, and then output onto an output terminal 17.
The pattern generating circuit 13 is for instance shown in FIG. 2 where clock pulses enter from a terminal 18 and counted by a K-bit binary counter 19. Using each count value of said binary counter 19 as an address, a memory (RAM or ROM) 21 of a capacity of 2.sup.k .times.2.sup.n bits is read out and then 2.sup.n pieces of parallel data (patterns) D1, D2, --, D2.sup.n are output. At that time, a delay time .tau..sub.0 exists from a rising edge of a clock at the terminal 18 to a conversion point (a node, namely a pattern data starting point for said clock) for a data of an output pattern generated in response to said edge. A PRBS (pseudo random binary sequence) generator, etc. may also be used in place of the memory 21.
The multiplexing circuit 14.sub.1 is shown in FIG. 3 for instance where odd-numbered parallel input patterns (Nos. 1, 3, --, 2.sup.n -1) among 2.sup.n parallel input patterns are supplied to gates G1, G3, --, G2.sup.n -1, while supplying even-numbered ones (Nos. 2, 4, --, 2.sup.n) to gates G2, G4, --, G2.sup.n. A clock signal of a duty of 50% is supplied from the terminal 23 directly into gates G1, G3, --, G2.sup.n -1 while said clock signal is inverted and supplied to gates G2, G4, --, G2.sup.n. Each gate G1, G3, --, G2.sup.n -1 to which the clock signal is directly supplied is paired respectively with other each gate G2, G4, --, G2.sup.n, and both outputs of each pair are supplied to each OR circuit R1, R2, --, R2.sup.n-1, respectively. Consequently, each OR circuit R1, R2, --, R2.sup.n-1 issues an odd-numbered input pattern data in the first half cycle of each clock, while in the latter half cycle even-numbered input pattern data being output. As a result, the input data is multiplexed into 2.sup.n-1 pieces of parallel pattern data. In this case, a delay time .tau..sub.1 exists from a rising edge of the clock at terminal 23 to each node of the output pattern data generated in response to said edge. The other multiplexing circuits 14.sub.2 -14.sub.n are composed also in the same principles, in which there are delay times .tau..sub.2 -.tau..sub.n, respectively. The operating frequency of each multiplexing circuit 14.sub.1 -14.sub.n becomes higher as the circuit is closer to the output terminal 17. Therefore, response of a multiplexing circuit is required to be higher where the circuit is closer to the output terminal 17, in normal cases. Consequently, a relationship EQU .tau..sub.0 &gt;.tau..sub.1 &gt;.tau..sub.2 &gt;--&gt;.tau..sub.n -- (1)
holds valid.
To create these delay times, the clock signals are delayed in the delay circuits 15.sub.1, 15.sub.2, --, 15.sub.n by delay times .tau..sub.1, .tau..sub.0 +.tau..sub.1, --, .tau..sub.0 +.tau..sub.1 +--+.tau..sub.n-1, respectively, which are supplied to the multiplexing circuit 14.sub.1, 14.sub.2, --, 14.sub.n as multiplexing control clock signals. In addition, the clock signal is delayed in the delay circuit 15.sub.r by .tau..sub.0 +.tau..sub.1 +--+.tau..sub.n +T.sub.0 and supplied to the retiming circuit 16.
Assuming that n=3 and the input clock signal at the terminal 11 in FIG. 1 is as shown in Row A of FIG. 4, the outputs of the frequency division circuits 12.sub.1, 12.sub.2 and 12.sub.3 become as shown in Rows B, C and D since the input clock signal CK is sequentially frequency divided by 2. In response to the clock pulse in Row D of FIG. 4, the output pattern of the pattern generating circuit 13 is delayed by .tau..sub.0 as shown in Row E of FIG. 4. Accordingly, the delay circuit 15.sub.1 is selected to have a delay .tau..sub.0, of which the output becomes as shown in Row F of FIG. 4. Since the output of the multiplexing circuit 14.sub.1 is delayed by .tau..sub.1 from the input as shown in Row G of FIG. 4, a delay of .tau..sub.0 +.tau..sub.1 is effected by the delay circuit 15.sub.2 as shown in Row H of FIG. 4. In the same way, the outputs of the multiplexing circuit 14.sub.2, delay circuit 15.sub.3, multiplexing circuit 14.sub.3, delay circuit 15.sub.r and the output terminal 17 become as shown in Rows I, J, K, L and M, respectively of FIG. 4. In FIGS. 1 and 4, each delay time of the 1/2 frequency division circuits 12.sub.1 -12.sub.3 and the retiming circuit 16 is assumed to be zero. However, a delay occurs actually in them. But, it is enough to consider the delays of the frequency dividers 12.sub.1 through 12.sub.n as included in the delays .tau..sub.1 through .tau..sub.n of the multiplexing circuits 14.sub.1 through 14.sub.n, respectively. The time T.sub.0 is selected normally to be a half of the data cycle of an output pattern when the input clock signal of the terminal 11 is made highest.
With the conventional pattern generator shown in FIG. 1, it is required to delay each output clock signal of the frequency division circuits 12.sub.1 -12.sub.n longer as the frequency is higher, and to supply the delayed clock signal to the related multiplexing circuit. The higher the frequency of the output pattern to be attempted, the more the number of the multiplexing circuits required. Correspondingly, the delay time of the delay circuit 15.sub.r becomes longer.
For instance, if it is attempted to obtain the output pattern of 10 GHz, .tau..sub.0 +--+.tau..sub.n reaches at least 40 ns. The delay circuit currently available to delay the clock signal of 10 GHz is only a coaxial cable whose delay time is 5 ns/m, so a cable length of 8 m is required for the delay of 40 ns. When a clock signal of a frequency as high as 10 GHz is to be applied into a coaxial cable, it is inevitable to insert amplifiers 26 at 2 m intervals along the coaxial cable 25. That is, in order to have the output pattern of 10 GHz, four 2 m pieces of coaxial cables and four amplifiers such as shown in FIG. 5 are required as the delay circuit 15.sub.r. Furthermore, since the signal is band restricted by the amplifiers 26, the waveform of the delayed output clock signal deteriorates so much as no correct retiming could be effected. In addition, the price also becomes higher.